期刊刊名：科學與工程技術期刊 　 卷期：1卷1期

篇名出版日期：2005年6月1日

作者：CHING-YUAN WU,吳慶源

語言：English

關鍵字：flash memory,split-gate,sidewall dielectric spacer,contactless flash memory array,critical mask steps,floating gate,快閃記憶體,分閘式,側邊牆介電墊層,無接點快閃記憶陣列,嚴謹罩幕步驟,漂浮閘

被點閱次數：7次

閱讀時間：109sec

摘要：
A scalable split-gate flash memory cell structure of the present invention comprises a common-source region, a scalable split-gate region formed by a sidewall dielectric spacer and a scalable common-drain region, wherein the scalable split-gate region comprising a floating-gate region being defined by another sidewall dielectric spacer has a tip-cathode line for erasing. The cell size of the present invention is scalable and can be made to be equal to 4F2 or smaller. The structure is then used to implement two contactless flash memory arrays: a contactless NOR-type flash memory array and a contactless parallel common-source/drain-conductive bit-lines flash memory array for high speed read/write/erase operations. Moreover, the contactless flash memory arrays can be fabricated with fewer critical masking steps as compared to the prior art.

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