期刊刊名：修平學報 　 卷期：28期

篇名出版日期：2014年3月1日

作者：余建政,Chien-Cheng Yu

語言：English

關鍵字：double edge-triggered flip-flop (DETFF), power consumption, power-delay product (PDP), single edge-triggered flip-flop (SETFF),雙邊緣觸發正反器,低功率損耗,功率延遲乘積,單邊緣觸發正反器

被點閱次數：3次

閱讀時間：19sec

摘要：
Low-power techniques are essential in modern CMOS VLSI design due to the continuous increase of clock frequency and chip complexity. In many applications, the power consumption of the IC clock system, composed of flip-flops and a clock distribution network, is one of the most power consuming subsystem in a CMOS VLSI circuit. As a consequence, the reduction of flip-flops power consumption is a crucial factor in IC design. In this paper, a new double edge-triggered flip-flop (DETFF) is presented in which power consumption is reduced. Several metrics are available for analysis of CMOS VLSI circuits, such as power consumption, delay, and power-delay product (PDP). In general, a PDP based metric is appropriate for low power portable systems. This paper compares three previously published DETFFs together with our design for their transistor counts, power consumption, and power-delay product. HSPICE simulation results employing TSMC 180nm CMOS technology indicate the proposed flip-flop can reduce effectively power consumption up to 39.62% and decrease power-delay product up to 76.78% respectively, as compared to other DETFFs.

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